RT-AC68R_CFE_1.0.1.8 台版

mty***

发现：
美版1.0.1.1版本的sdram_config=0x0147
台版1.0.1.8版本的sdram_config=0x0149 这个版本的无线功率=25dBm 320mW
有没有谁知道是怎么回事？

hana***

下下来，研究一下

zhj***

# for 4707/8/9
# Only sdram_config is used. It is a 16-bit number.
# Bits   Definition
# -----  -----------------------------------------------------------------------------------------------------------
# 15:11  Reserved
#  10:8  Column Size: 000 = 2048 columns; 001 = 1024 columns; 010 = 512 columns
#   7    0 = 16 bit wide data bus; 1 = 8 bit wide data bus
#   6    0 = 4 banks; 1 = 8 banks
#            NOTE: For 4 banks, columns can be 512, 1024, or 2048. For 8 banks, columns can only be 1024 or 2048.
#  5:3   Reserved
#  2:0   CAS latency: 011 = CL is 3; 100 = CL is 4; 101 = CL is 5; 110 = CL is 6; 111 = CL is 7; all others reserved
#
# Set 64MB (1Gbit) of DDR3 (DDR64X16), x16, 8 banks, CL=7
sdram_config=0x0149

# For 4707/8/9 - Required to set the DDR PHY clock correctly *before* the boot code is copied to DDR. Since the NVRAM
# parsing is done after the execution is passed to DDR, the DDR PHY clock must be reconfigured from its default of
# 333MHz. The "sdram_ncdl" parameter is stored in a fixed location in the CFE space, so the bootloader can read it while
# still executing from flash. This is a limitation of the way the DDR PHY clock reconfiguration occurs on 4707/8/9 parts.
#
# Set DDR3 clock of 533MHz (800MT/s) for RT-AC68U
#sdram_ncdl=533