TTL如下:有root密码。尝试过几个常用的无法登录
MT7621 stage1 code Jul 31 2020 21:08:21 (ASIC)
CPU=50000000 HZ BUS=16666666 HZ
==================================================================
MT7621 set GPIO3/4 for TP-link
Change MPLL source from XTAL to CR...
do MEMPLL setting..
MEMPLL Config : 0x11100000
3PLL mode + External loopback
=== XTAL-40Mhz === DDR-1200Mhz ===
PLL3 FB_DL: 0x8, 1/0 = 614/410 21000000
PLL2 FB_DL: 0x10, 1/0 = 611/413 41000000
PLL4 FB_DL: 0x13, 1/0 = 560/464 4D000000
DDR patch working
do DDR setting..[00320381]
Apply DDR3 Setting...(use customer AC)
0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120
--------------------------------------------------------------------------------
0000:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0001:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0002:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0003:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0004:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0005:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0006:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0007:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0008:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0009:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000A:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000B:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000C:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000D:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000E:| 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
000F:| 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0
0010:| 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0
0011:| 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0
0012:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0013:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0014:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0015:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0016:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0017:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0018:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0019:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001A:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001B:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001C:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001D:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001E:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001F:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DRAMC_DQSCTL1[0e0]=14000000
DRAMC_DQSGCTL[124]=80000000
rank 0 coarse = 16
rank 0 fine = 40
B:| 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0
opt_dle value:9
DRAMC_DDR2CTL[07c]=C287221D
DRAMC_PADCTL4[0e4]=000022B3
DRAMC_DQIDLY1[210]=0D0A0B0B
DRAMC_DQIDLY2[214]=080A090A
DRAMC_DQIDLY3[218]=0F0B0A0A
DRAMC_DQIDLY4[21c]=0C090D0B
DRAMC_R0DELDLY[018]=00001E1E
==================================================================
RX DQS perbit delay software calibration
==================================================================
1.0-15 bit dq delay value
==================================================================
bit| 0 1 2 3 4 5 6 7 8 9
--------------------------------------
0 | 10 11 9 13 9 9 9 8 8 9
10 | 10 13 10 11 9 10
--------------------------------------
==================================================================
2.dqs window
x=pass dqs delay value (min~max)center
y=0-7bit DQ of every group
input delay QS0 =30 DQS1 = 30
==================================================================
bit DQS0 bit DQS1
0 (1~58)29 8 (1~55)28
1 (1~60)30 9 (1~57)29
2 (1~57)29 10 (1~57)29
3 (1~60)30 11 (1~56)28
4 (1~58)29 12 (1~57)29
5 (1~60)30 13 (1~56)28
6 (1~58)29 14 (1~59)30
7 (1~60)30 15 (1~56)28
==================================================================
3.dq delay value last
==================================================================
bit| 0 1 2 3 4 5 6 7 8 9
--------------------------------------
0 | 11 11 10 13 10 9 10 8 10 10
10 | 11 15 11 13 9 12
==================================================================
==================================================================
TX perbyte calibration
==================================================================
DQS loop = 15, cmp_err_1 = ffff2000
dqs_perbyte_dly.last_dqsdly_pass[0]=15, finish count=1
DQS loop = 14, cmp_err_1 = ffff0000
dqs_perbyte_dly.last_dqsdly_pass[1]=14, finish count=2
DQ loop=15, cmp_err_1 = ffff0080
dqs_perbyte_dly.last_dqdly_pass[1]=15, finish count=1
DQ loop=14, cmp_err_1 = ffff0000
dqs_perbyte_dly.last_dqdly_pass[0]=14, finish count=2
byte:0, (DQS,DQ)=(8,8)
byte:1, (DQS,DQ)=(8,8)
DRAMC_DQODLY1[200]=88888888
DRAMC_DQODLY2[204]=88888888
20,data:88
[EMI] DRAMC calibration passed
===================================================================
MT7621 stage1 code done
CPU=50000000 HZ BUS=16666666 HZ
===================================================================
U-Boot 1.1.3 (Jan 29 2021 - 16:28:19)
Board: Ralink APSoC DRAM: 256 MB
relocate_code Pointer at: 8ff98000
set ALL LAN Partition
Config XHCI 40M PLL
******************************
Software System Reset Occurred
******************************
Allocate 16 byte aligned buffer: 8ffe0750
Enable NFI Clock
# MTK NAND # : Use HW ECC
NAND ID [C8 D1 80 95 40]
Device not found, ID: c8d1
Not Support this Device!
chip_mode=00000001
Support this Device in MTK table! c8d1
select_chip
[NAND]select ecc bit:4, sparesize :64 spare_per_sector=16
Signature matched and data read!
load_fact_bbt success 1023
load fact bbt success
[mtk_nand] probe successfully!
mtd->writesize=2048 mtd->oobsize=64, mtd->erasesize=131072 devinfo.iowidth=8
.*** Warning - bad CRC, using default environment
Press reset button to enter recovery mode.
Autobooting in 300 ms
Dual image validation, to check image_2 now
#Reset_MT7530
verifying uboot partition...
..ok
verifying kernel and romfs partition...
................................................................................................................................................................ok
..normal boot offset = 4585000, size = 20000
..To boot, bootcmd = bootm 0xa0800000.
..normal boot offset = 4585000, size = 20000
..
U-Boot 1.1.3 (Feb 5 2021 - 23:11:27)
Board: Ralink APSoC DRAM: 256 MB
relocate_code Pointer at: 8ffb0000
Config XHCI 40M PLL
Allocate 16 byte aligned buffer: 8ffe0530
Enable NFI Clock
# MTK NAND # : Use HW ECC
NAND ID [C8 D1 80 95 40]
Device not found, ID: c8d1
Not Support this Device!
chip_mode=00000001
Support this Device in MTK table! c8d1
select_chip
[NAND]select ecc bit:4, sparesize :64 spare_per_sector=16
Signature matched and data read!
load_fact_bbt success 1023
load fact bbt success
[mtk_nand] probe successfully!
mtd->writesize=2048 mtd->oobsize=64, mtd->erasesize=131072 devinfo.iowidth=8
.*** Warning - bad CRC, using default environment
============================================
Ralink UBoot Version: 4.3.S.0
--------------------------------------------
ASIC MT7621A DualCore (MAC to MT7530 Mode)
DRAM_CONF_FROM: Auto-Detection
DRAM_TYPE: DDR3
DRAM bus: 16 bit
Xtal Mode=3 OCP Ratio=1/3
Flash component: NAND Flash
Date:Feb 5 2021 Time:23:11:27
============================================
icache: sets:256, ways:4, linesz:32 ,total:32768
dcache: sets:256, ways:4, linesz:32 ,total:32768
##### The CPU freq = 880 MHZ ####
estimate memory size =256 Mbytes
#Reset_MT7530
set ALL LAN Partition
Booting image_2(kernel_2)Copying kernel(include tpHeader) from flash 0x46c0000 to RAM 0x86000000To boot and runcmd bootm 0x46c0000.
Autobooting in 0 ms
## Booting image at 046c0000 ...
addr:0x046c0000
................................................................---- tpHdr = 8feb11f0
---- text base = 81001000
---- entry point = 81001000
Uncompressing Kernel Image ... OK
No initrd
## Transferring control to Linux (at address 81001000) ...
## Giving linux memsize in MB, 256
Starting kernel ... |