新版N2N_V2+LUCI（全平台）

小正

收藏了。谢谢楼主分享

small_5

lhx11187 发表于 2017-11-20 12:18
P2P的穿透太难，我是移动大内网，都是需要转发的，可以用zerotier

移动不清楚，我这电信和联通都是内网ip的情况下可以穿，因为2边都是nat2。移动只要出口不做nat应该也是nat2才对。

small_5

而且zerotier跟n2n原理差不多的，就是一个服务端自己的，一个第三方的，能否穿透就由2边nat类型决定

rwshui

还没测试，准备试一下n2n。请问下那个新参数 添加本地IP是什么个用法和意思？，不太理解，可否举个例子？

hello_limin

small_5 发表于 2017-11-14 12:08
同城电信+联通的延迟，还行，上行也可以跑满，旧版本的在我这儿打不起洞。

相关源代码，

1. /*
   
2. *  TP-LINK TL-WR881N v1 board support
   
3. *
   
4. *  Copyright (C) 2016 Alexander Wang <limin2016@yahoo.com>
   
5. *  Copyright (C) 2015 Weijie Gao <hackpacsal@gmail.com>
   
6. *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
   
7. *
   
8. *  This program is free software; you can redistribute it and/or modify it
   
9. *  under the terms of the GNU General Public License version 2 as published
   
10. *  by the Free Software Foundation.
    
11. */
    
12. 
    
13. #include <linux/pci.h>
    
14. #include <linux/phy.h>
    
15. #include <linux/gpio.h>
    
16. #include <linux/delay.h>
    
17. #include <linux/mtd/mtd.h>
    
18. #include <linux/mtd/partitions.h>
    
19. #include <linux/platform_device.h>
    
20. #include <linux/ath9k_platform.h>
    
21. #include <linux/ar8216_platform.h>
    
22. 
    
23. #include <asm/mach-ath79/ath79.h>
    
24. #include <asm/mach-ath79/ar71xx_regs.h>
    
25. 
    
26. #include "pci.h"
    
27. #include "common.h"
    
28. #include "dev-ap9x-pci.h"
    
29. #include "dev-eth.h"
    
30. #include "dev-gpio-buttons.h"
    
31. #include "dev-leds-gpio.h"
    
32. #include "dev-m25p80.h"
    
33. #include "dev-spi.h"
    
34. #include "dev-wmac.h"
    
35. #include "machtypes.h"
    
36. 
    
37. #define WR881NV1_GPIO_LED_WLAN  12
    
38. #define WR881NV1_GPIO_LED_SYSTEM  19
    
39. #define WR881NV1_GPIO_LED_WPS 15
    
40. 
    
41. #define WR881NV1_GPIO_BTN_RESET 16
    
42. 
    
43. #define WR881NV1_KEYS_POLL_INTERVAL 20        /* msecs */
    
44. #define WR881NV1_KEYS_DEBOUNCE_INTERVAL (3 * WR881NV1_KEYS_POLL_INTERVAL)
    
45. 
    
46. #define ATH_MII_MGMT_CMD  0x24
    
47. #define ATH_MGMT_CMD_READ 0x1
    
48. 
    
49. #define ATH_MII_MGMT_ADDRESS  0x28
    
50. #define ATH_ADDR_SHIFT  8
    
51. 
    
52. #define ATH_MII_MGMT_CTRL 0x2c
    
53. #define ATH_MII_MGMT_STATUS 0x30
    
54. 
    
55. #define ATH_MII_MGMT_IND  0x34
    
56. #define ATH_MGMT_IND_BUSY (1 << 0)
    
57. #define ATH_MGMT_IND_INVALID  (1 << 2)
    
58. 
    
59. #define WR881NV1_WMAC_CALDATA_OFFSET  0x1000
    
60. 
    
61. #define QCA955X_ETH_CFG_GMAC0_EN  BIT(1)
    
62. #define QCA955X_ETH_CFG_GMAC0_SLAVE BIT(4)
    
63. 
    
64. static const char *wr881nv1_part_probes[] = {
    
65.         "tp-link",
    
66.         NULL,
    
67. };
    
68. 
    
69. static struct flash_platform_data wr881nv1_flash_data = {
    
70.         .part_probes        = wr881nv1_part_probes,
    
71. };
    
72. 
    
73. static struct gpio_led wr881nv1_leds_gpio[] __initdata = {
    
74.         {
    
75.                 .name                = "tp-link:green:wps",
    
76.                 .gpio                = WR881NV1_GPIO_LED_WPS,
    
77.                 .active_low        = 1,
    
78.         },
    
79.         {
    
80.                 .name                = "tp-link:green:system",
    
81.                 .gpio                = WR881NV1_GPIO_LED_SYSTEM,
    
82.                 .active_low        = 1,
    
83.         },
    
84.         {
    
85.                 .name                = "tp-link:green:wlan",
    
86.                 .gpio                = WR881NV1_GPIO_LED_WLAN,
    
87.                 .active_low        = 1,
    
88.         },
    
89. };
    
90. 
    
91. static struct gpio_keys_button wr881nv1_gpio_keys[] __initdata = {
    
92.         {
    
93.                 .desc                = "reset",
    
94.                 .type                = EV_KEY,
    
95.                 .code                = KEY_RESTART,
    
96.                 .debounce_interval = WR881NV1_KEYS_DEBOUNCE_INTERVAL,
    
97.                 .gpio                = WR881NV1_GPIO_BTN_RESET,
    
98.                 .active_low        = 1,
    
99.         },
    
100. };
     
101. 
     
102. static struct mdio_board_info wr881nv1_mdio0_info[] = {
     
103.         {
     
104.                 .bus_id = "ag71xx-mdio.0",
     
105.                 .phy_addr = 0,
     
106.                 .platform_data = NULL,
     
107.         },
     
108. };
     
109. 
     
110. static unsigned long __init ath_gmac_reg_rd(unsigned long reg)
     
111. {
     
112.         void __iomem *base;
     
113.         unsigned long t;
     
114. 
     
115.         base = ioremap(AR71XX_GE0_BASE, AR71XX_GE0_SIZE);
     
116. 
     
117.         t = __raw_readl(base + reg);
     
118. 
     
119.         iounmap(base);
     
120. 
     
121.         return t;
     
122. }
     
123. 
     
124. static void __init ath_gmac_reg_wr(unsigned long reg, unsigned long value)
     
125. {
     
126.         void __iomem *base;
     
127.         unsigned long t = value;
     
128. 
     
129.         base = ioremap(AR71XX_GE0_BASE, AR71XX_GE0_SIZE);
     
130. 
     
131.         __raw_writel(t, base + reg);
     
132. 
     
133.         iounmap(base);
     
134. }
     
135. 
     
136. static void __init phy_reg_write(unsigned char phy_addr, unsigned char reg, unsigned short data)
     
137. {
     
138.         unsigned short addr = (phy_addr << ATH_ADDR_SHIFT) | reg;
     
139.         volatile int rddata;
     
140.         unsigned short ii = 0xFFFF;
     
141. 
     
142.         do
     
143.         {
     
144.                 udelay(5);
     
145.                 rddata = ath_gmac_reg_rd(ATH_MII_MGMT_IND) & 0x1;
     
146.         } while (rddata && --ii);
     
147. 
     
148.         ath_gmac_reg_wr(ATH_MII_MGMT_ADDRESS, addr);
     
149.         ath_gmac_reg_wr(ATH_MII_MGMT_CTRL, data);
     
150. 
     
151.         do
     
152.         {
     
153.                 udelay(5);
     
154.                 rddata = ath_gmac_reg_rd(ATH_MII_MGMT_IND) & 0x1;
     
155.         } while (rddata && --ii);
     
156. }
     
157. 
     
158. static unsigned short __init phy_reg_read(unsigned char phy_addr, unsigned char reg)
     
159. {
     
160.         unsigned short addr = (phy_addr << ATH_ADDR_SHIFT) | reg, val;
     
161.         volatile int rddata;
     
162.         unsigned short ii = 0xffff;
     
163. 
     
164.         do
     
165.         {
     
166.                 udelay(5);
     
167.                 rddata = ath_gmac_reg_rd(ATH_MII_MGMT_IND) & 0x1;
     
168.         } while (rddata && --ii);
     
169. 
     
170.         ath_gmac_reg_wr(ATH_MII_MGMT_CMD, 0x0);
     
171.         ath_gmac_reg_wr(ATH_MII_MGMT_ADDRESS, addr);
     
172.         ath_gmac_reg_wr(ATH_MII_MGMT_CMD, ATH_MGMT_CMD_READ);
     
173. 
     
174.         do
     
175.         {
     
176.                 udelay(5);
     
177.                 rddata = ath_gmac_reg_rd(ATH_MII_MGMT_IND) & 0x1;
     
178.         } while (rddata && --ii);
     
179. 
     
180.         val = ath_gmac_reg_rd(ATH_MII_MGMT_STATUS);
     
181.         ath_gmac_reg_wr(ATH_MII_MGMT_CMD, 0x0);
     
182. 
     
183.         return val;
     
184. }
     
185. 
     
186. static void __init athrs27_reg_write(unsigned int s27_addr, unsigned int s27_write_data)
     
187. {
     
188.         unsigned int addr_temp;
     
189.         unsigned int data;
     
190.         unsigned char phy_address, reg_address;
     
191. 
     
192.         addr_temp = (s27_addr) >> 2;
     
193.         data = addr_temp >> 7;
     
194. 
     
195.         phy_address = 0x1f;
     
196.         reg_address = 0x10;
     
197. 
     
198.         phy_reg_write(phy_address, reg_address, data);
     
199. 
     
200.         phy_address = (0x17 & ((addr_temp >> 4) | 0x10));
     
201. 
     
202.         reg_address = (((addr_temp << 1) & 0x1e) | 0x1);
     
203.         data = (s27_write_data >> 16) & 0xffff;
     
204.         phy_reg_write(phy_address, reg_address, data);
     
205. 
     
206.         reg_address = ((addr_temp << 1) & 0x1e);
     
207.         data = s27_write_data  & 0xffff;
     
208.         phy_reg_write(phy_address, reg_address, data);
     
209. }
     
210. 
     
211. static unsigned int __init athrs27_reg_read(unsigned int s27_addr)
     
212. {
     
213.         unsigned int addr_temp;
     
214.         unsigned int s27_rd_csr_low, s27_rd_csr_high, s27_rd_csr;
     
215.         unsigned int data;
     
216.         unsigned char phy_address, reg_address;
     
217. 
     
218.         addr_temp = s27_addr >>2;
     
219.         data = addr_temp >> 7;
     
220. 
     
221.         phy_address = 0x1f;
     
222.         reg_address = 0x10;
     
223. 
     
224.         phy_reg_write(phy_address, reg_address, data);
     
225. 
     
226.         phy_address = (0x17 & ((addr_temp >> 4) | 0x10));
     
227.         reg_address = ((addr_temp << 1) & 0x1e);
     
228.         s27_rd_csr_low = (unsigned int) phy_reg_read(phy_address, reg_address);
     
229. 
     
230.         reg_address = reg_address | 0x1;
     
231.         s27_rd_csr_high = (unsigned int) phy_reg_read(phy_address, reg_address);
     
232.         s27_rd_csr = (s27_rd_csr_high << 16) | s27_rd_csr_low ;
     
233.        
     
234.         return (s27_rd_csr);
     
235. }
     
236. 
     
237. static void __init ar8236_reset(void)
     
238. {
     
239.         unsigned short i = 30;
     
240. 
     
241.         athrs27_reg_write(0x0, athrs27_reg_read(0x0) | 0x80000000);
     
242.         while (i--)
     
243.         {
     
244.                 mdelay(100);
     
245.                 if (!(athrs27_reg_read(0x0) & 0x80000000))
     
246.                 break;
     
247.         }
     
248. }
     
249. 
     
250. static void __init wr881nv1_setup(void)
     
251. {
     
252.         u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
     
253.         u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
     
254.         u8 tmpmac[ETH_ALEN];
     
255. 
     
256.         ath79_register_m25p80(&wr881nv1_flash_data);
     
257.        
     
258.         ath79_register_pci();
     
259.        
     
260.         ath79_init_mac(tmpmac, mac, 0);
     
261.         ath79_register_wmac(art + WR881NV1_WMAC_CALDATA_OFFSET, tmpmac);
     
262. 
     
263.         ath79_register_mdio(0, 0x0);
     
264.        
     
265.         mdiobus_register_board_info(wr881nv1_mdio0_info,
     
266.                                     ARRAY_SIZE(wr881nv1_mdio0_info));
     
267. 
     
268.         ar8236_reset();
     
269.        
     
270.         ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_GMAC0_EN | QCA955X_ETH_CFG_GMAC0_SLAVE);
     
271.   
     
272.         /* WAN */
     
273.         ath79_register_eth(1);
     
274.         ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1);
     
275. 
     
276.         /* GMAC0 is connected to the PHY0 of the AR8236 switch, GE0 */
     
277.         ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
     
278.         ath79_eth1_data.duplex = DUPLEX_FULL;
     
279.         ath79_eth1_data.speed = SPEED_100;
     
280.         ath79_eth1_data.phy_mask = BIT(0);
     
281.         ath79_eth1_data.mii_bus_dev = &ath79_mdio0_device.dev;
     
282.        
     
283.         ath79_register_leds_gpio(-1, ARRAY_SIZE(wr881nv1_leds_gpio),
     
284.                                  wr881nv1_leds_gpio);
     
285.         ath79_register_gpio_keys_polled(-1, WR881NV1_KEYS_POLL_INTERVAL,
     
286.                                         ARRAY_SIZE(wr881nv1_gpio_keys),
     
287.                                         wr881nv1_gpio_keys);
     
288. }
     
289. 
     
290. MIPS_MACHINE(ATH79_MACH_TL_WR881N_V1, "TL-WR881N-v1", "TP-LINK TL-WR881N v1", wr881nv1_setup);

复制代码

yueke

编译N2N出错是怎么回事？
make[4]: Entering directory '/home/LEDE/source/build_dir/target-mips_24kc_musl/n2n-svn5633'
make[4]: *** No targets specified and no makefile found.  Stop.

zshwq5

感谢分享，可以正常编译了。

diannaojiang

感谢楼主编译。试试能不能用在k3上

n5413

奇怪了，为何我编译总是报错，提示没找到源码里的makefile文件，这要怎么弄?搭建服务端搞不了啊，对比了下官网旧版源码，这个新版源码目录的确没有makefile文件，求解啊!

small_5

n5413 发表于 2017-12-5 01:13
奇怪了，为何我编译总是报错，提示没找到源码里的makefile文件，这要怎么弄?搭建服务端搞不了啊，对比了下 ...

apt-get install subversion build-essential libssl-dev
git clone https://github.com/meyerd/n2n.git
cd n2n/n2n_v2
mkdir build
cd build
cmake ..
make
sudo make install

oso21

能否提供n2n的makefile，我想加入自己的固件，谢谢

n5413

small_5 发表于 2017-12-5 05:45
apt-get install subversion build-essential libssl-dev
git clone https://github.com/meyerd/n2n.git ...

原来如此，成功了，太感谢了，不过这个编译这么麻烦，那编译openwrt版本的makefile也要修改吧？能否指点一二，我想给openwrt 15.05编译一份。

small_5

n5413 发表于 2017-12-5 14:30
原来如此，成功了，太感谢了，不过这个编译这么麻烦，那编译openwrt版本的makefile也要修改吧？能否指点 ...

郵箱發給我吧

mjyhj

4.9.65内核装不了，mips，3800，lede

lucktu

small_5 发表于 2017-11-16 12:04
晚点我会加入的。

建议楼主把v1也编辑出来，因为他也有小部分更新的。

另外，如果方便，请把padavan的也编辑出来