【2018年03月20日】分享自用 wr881n-v1 的番羽墻固件纯洁版嘿嘿 *^_^*

unffe · 发表于 2018-3-25 22:34

弱弱问下有4M的吗。。。

royalwei · 发表于 2018-3-25 22:48

看看，谢谢分享

a731152739 · 发表于 2018-3-25 23:49

6666666666大佬

hello_limin · 发表于 2018-3-31 14:01

本帖最后由 hello_limin 于 2018-4-7 11:46 编辑

/* D-Link DIR-869 A1 support.
*
* Copyright (C) 2015-2016 P. Wassi <p.wassi at gmx.at>
* Copyright (C) 2017 Matthias Schiffer <mschiffer@universe-factory.net>
*
* Derived from: TP-Link Archer C60 v2 board.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/phy.h>
#include <linux/platform_device.h>
#include <linux/ath9k_platform.h>
#include <asm/mach-ath79/ath79.h>
#include <asm/mach-ath79/irq.h>
#include <asm/mach-ath79/ar71xx_regs.h>
#include <linux/platform_data/phy-at803x.h>
#include <linux/ar8216_platform.h>
#include "common.h"
#include "dev-spi.h"
#include "dev-eth.h"
#include "dev-gpio-buttons.h"
#include "dev-leds-gpio.h"
#include "dev-m25p80.h"
#include "dev-wmac.h"
#include "machtypes.h"
#define DIR869A1_GPIO_BTN_RESET 16
#define DIR869A1_GPIO_LED_POWER 19
#define DIR869A1_GPIO_LED_WPS 15
#define DIR869A1_KEYS_POLL_INTERVAL 20 /* msecs */
#define DIR869A1_KEYS_DEBOUNCE_INTERVAL (3 * DIR869A1_KEYS_POLL_INTERVAL)
#define DIR869A1_DEVDATA_ADDR 0x1f01fc00
#define DIR869A1_EEPROM_ADDR 0x1fff0000
#define DIR869A1_WMAC_CALDATA_OFFSET 0x1000
#define DIR869A1_PCI_CALDATA_OFFSET 0x5000
#define ATH_MII_MGMT_CMD 0x24
#define ATH_MGMT_CMD_READ 0x1
#define ATH_MII_MGMT_ADDRESS 0x28
#define ATH_ADDR_SHIFT 8
#define ATH_MII_MGMT_CTRL 0x2c
#define ATH_MII_MGMT_STATUS 0x30
#define ATH_MII_MGMT_IND 0x34
#define ATH_MGMT_IND_BUSY (1 << 0)
#define ATH_MGMT_IND_INVALID (1 << 2)
#define QCA955X_ETH_CFG_GE0_MII_EN BIT(1)
#define QCA955X_ETH_CFG_GE0_MII_SLAVE BIT(4)
static const char *dir869a1_part_probes[] = {
"tp-link",
NULL,
};
static struct flash_platform_data dir869a1_flash_data = {
.part_probes = dir869a1_part_probes,
};
static struct gpio_led dir869a1_leds_gpio[] __initdata = {
{
.name = "tp-link:green:system",
.gpio = DIR869A1_GPIO_LED_POWER,
.active_low = 1,
},
{
.name = "tp-link:green:wps",
.gpio = DIR869A1_GPIO_LED_WPS,
.active_low = 1,
},
};
static struct gpio_keys_button dir869a1_gpio_keys[] __initdata = {
{
.desc = "reset",
.type = EV_KEY,
.code = KEY_RESTART,
.debounce_interval = DIR869A1_KEYS_DEBOUNCE_INTERVAL,
.gpio = DIR869A1_GPIO_BTN_RESET,
.active_low = 1,
},
};
static struct mdio_board_info dir869a1_mdio0_info[] = {
{
.bus_id = "ag71xx-mdio.0",
.phy_addr = 0,
.platform_data = NULL,
},
};
static unsigned long __init ath_gmac_reg_rd(unsigned long reg)
{
void __iomem *base;
unsigned long t;
base = ioremap(AR71XX_GE0_BASE, AR71XX_GE0_SIZE);
t = __raw_readl(base + reg);
iounmap(base);
return t;
}
static void __init ath_gmac_reg_wr(unsigned long reg, unsigned long value)
{
void __iomem *base;
unsigned long t = value;
base = ioremap(AR71XX_GE0_BASE, AR71XX_GE0_SIZE);
__raw_writel(t, base + reg);
iounmap(base);
}
static void __init phy_reg_write(unsigned char phy_addr, unsigned char reg, unsigned short data)
{
unsigned short addr = (phy_addr << ATH_ADDR_SHIFT) | reg;
volatile int rddata;
unsigned short ii = 0xFFFF;
do
{
udelay(5);
rddata = ath_gmac_reg_rd(ATH_MII_MGMT_IND) & 0x1;
} while (rddata && --ii);
ath_gmac_reg_wr(ATH_MII_MGMT_ADDRESS, addr);
ath_gmac_reg_wr(ATH_MII_MGMT_CTRL, data);
do
{
udelay(5);
rddata = ath_gmac_reg_rd(ATH_MII_MGMT_IND) & 0x1;
} while (rddata && --ii);
}
static unsigned short __init phy_reg_read(unsigned char phy_addr, unsigned char reg)
{
unsigned short addr = (phy_addr << ATH_ADDR_SHIFT) | reg, val;
volatile int rddata;
unsigned short ii = 0xffff;
do
{
udelay(5);
rddata = ath_gmac_reg_rd(ATH_MII_MGMT_IND) & 0x1;
} while (rddata && --ii);
ath_gmac_reg_wr(ATH_MII_MGMT_CMD, 0x0);
ath_gmac_reg_wr(ATH_MII_MGMT_ADDRESS, addr);
ath_gmac_reg_wr(ATH_MII_MGMT_CMD, ATH_MGMT_CMD_READ);
do
{
udelay(5);
rddata = ath_gmac_reg_rd(ATH_MII_MGMT_IND) & 0x1;
} while (rddata && --ii);
val = ath_gmac_reg_rd(ATH_MII_MGMT_STATUS);
ath_gmac_reg_wr(ATH_MII_MGMT_CMD, 0x0);
return val;
}
static void __init athrs27_reg_write(unsigned int s27_addr, unsigned int s27_write_data)
{
unsigned int addr_temp;
unsigned int data;
unsigned char phy_address, reg_address;
addr_temp = (s27_addr) >> 2;
data = addr_temp >> 7;
phy_address = 0x1f;
reg_address = 0x10;
phy_reg_write(phy_address, reg_address, data);
phy_address = (0x17 & ((addr_temp >> 4) | 0x10));
reg_address = (((addr_temp << 1) & 0x1e) | 0x1);
data = (s27_write_data >> 16) & 0xffff;
phy_reg_write(phy_address, reg_address, data);
reg_address = ((addr_temp << 1) & 0x1e);
data = s27_write_data & 0xffff;
phy_reg_write(phy_address, reg_address, data);
}
static unsigned int __init athrs27_reg_read(unsigned int s27_addr)
{
unsigned int addr_temp;
unsigned int s27_rd_csr_low, s27_rd_csr_high, s27_rd_csr;
unsigned int data;
unsigned char phy_address, reg_address;
addr_temp = s27_addr >>2;
data = addr_temp >> 7;
phy_address = 0x1f;
reg_address = 0x10;
phy_reg_write(phy_address, reg_address, data);
phy_address = (0x17 & ((addr_temp >> 4) | 0x10));
reg_address = ((addr_temp << 1) & 0x1e);
s27_rd_csr_low = (unsigned int) phy_reg_read(phy_address, reg_address);
reg_address = reg_address | 0x1;
s27_rd_csr_high = (unsigned int) phy_reg_read(phy_address, reg_address);
s27_rd_csr = (s27_rd_csr_high << 16) | s27_rd_csr_low ;
return (s27_rd_csr);
}
static void __init ar8236_reset(void)
{
unsigned short i = 30;
athrs27_reg_write(0x0, athrs27_reg_read(0x0) | 0x80000000);
while (i--)
{
mdelay(100);
if (!(athrs27_reg_read(0x0) & 0x80000000))
break;
}
}
static void __init dir869a1_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(DIR869A1_DEVDATA_ADDR);
u8 *art = (u8 *) KSEG1ADDR(DIR869A1_EEPROM_ADDR);
u8 tmpmac[ETH_ALEN];
ath79_register_m25p80(&dir869a1_flash_data);
ar8236_reset();
ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_GE0_MII_EN |
QCA955X_ETH_CFG_GE0_MII_SLAVE);
ath79_register_mdio(0, 0x0);
mdiobus_register_board_info(dir869a1_mdio0_info,
ARRAY_SIZE(dir869a1_mdio0_info));
ath79_init_mac(tmpmac, mac, 2);
ath79_register_wmac(art + DIR869A1_WMAC_CALDATA_OFFSET, tmpmac);
/* WAN port */
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
/* GMAC0 is connected to the PHY0 of the internal switch */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_data.speed = SPEED_100;
ath79_eth0_data.duplex = DUPLEX_FULL;
ath79_eth0_data.phy_mask = BIT(0);
ath79_register_eth(0);
/* Actually, this GPIO controls the LED power,
* while d-link:orange:status switches it between
* orange and white */
ath79_register_leds_gpio(-1, ARRAY_SIZE(dir869a1_leds_gpio),
dir869a1_leds_gpio);
ath79_register_gpio_keys_polled(-1, DIR869A1_KEYS_POLL_INTERVAL,
ARRAY_SIZE(dir869a1_gpio_keys),
dir869a1_gpio_keys);
}
MIPS_MACHINE(ATH79_MACH_TL_WR881ND_V1, "TL-WR881ND-V1", "TP-Link TL-WR881N/ND rev. A1", dir869a1_setup);

复制代码

enenenen · 发表于 2018-4-2 13:19

中继怎么样？

火鸟 · 发表于 2018-4-2 14:06

不错啊，下载下来看看效果如何

特立独行的墙 · 发表于 2018-4-2 15:41

感觉很牛逼呀，先收藏了

jie8689819 · 发表于 2018-4-2 16:00

看看是什么

何太清 · 发表于 2018-4-10 12:24

自动fan greatwall?有木有账号啊

小城印象 · 发表于 2018-4-11 01:44

地址没隐藏啊

hello_limin · 发表于 2018-4-14 20:32

小城印象发表于 2018-4-11 01:44
地址没隐藏啊

隐藏了啊你再看看？

safehorse · 发表于 2018-4-14 22:32

老大，我有个941ND-V6 （当然是CN版）, 机器是4M的，是不是SS或者S.SR是死活搞不进去的?

因为要搞S-S也不单纯是S-S一个, 肯定还需要那个 CHINA-LIST或者CHNROUTE, 单纯这个文件就大概有100多K了。

safehorse · 发表于 2018-4-14 22:33

即使是现在LEDE出现的那个FOR SMALL FLASH机器那一个TARGET，也是搞不定啊,编译试了下根本少不了多少体积

ykglove · 发表于 2018-4-14 22:38

这负载能用愉快网上冲浪吗

safehorse · 发表于 2018-4-14 22:39

不需要UPNP, 不需要KMS, 能有LUCI界面,服务有S.SR方案或者S.S+china-dns方案， 941NDV6 4M 能编译的出来么老大

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【2018年03月20日】分享自用 wr881n-v1 的番羽墻固件纯洁版嘿嘿 ^_^

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【2018年03月20日】分享自用 wr881n-v1 的 番羽 墻 固件 纯洁版 嘿嘿 *^_^*

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【2018年03月20日】分享自用 wr881n-v1 的番羽墻固件纯洁版嘿嘿 ^_^