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本帖最后由 snowlxylxy 于 2021-3-15 15:41 编辑
接上个K2P变砖的帖子https://www.right.com.cn/forum/thread-4091247-1-1.html,又用TTL测试了一下,这是刷了Bbreed后输出信息如下,跑完就不跑了
Boot and Recovery Environment for Embedded Devices
Copyright (C) 2020 HackPascal <hackpascal@gmail.com>
Build date 2020-10-09 [git-676bfd4]
Version 1.1 (r1286)
DRAM: 128MB
Platform: MediaTek MT7621A ver 1, eco 3
Board: Phicomm K2P
Clocks: CPU: 880MHz, DDR: 1200MHz, Bus: 220MHz, Ref: 40MHz
Flash: GigaDevice GD25Q128 (16MB) on mt7621-spi.0
rt2880-eth: MAC address from EEPROM is invalid, using default settings.
rt2880-eth: Using MAC address 00:0c:43:00:00:01
eth0: MediaTek MT7530 Gigabit switch
Network started on eth0, inet addr 192.168.1.1, netmask 255.255.255.0
Press any key to interrupt autoboot ... 0
Trying to boot firmware from 0x000a0000 in flash bank 0 ...
Reading data into memory ...
U-Boot firmware image header detected.
Image Name: OpenWrt-Linux-3.10.14
Data Size: 3278959 Bytes
Load Address: 81001000
Entry Point: 81001000
Uncompressing data (LZMA) ... done.
Flushing cache ... done.
Starting kernel at 0x81001000...
LINUX started...
THIS IS ASIC
SDK 5.0.S.0
[ 0.000000] Linux version 3.10.14 (jenkins@SOHO-OPWRT) (gcc version 4.8.3 (OpenWrt/Linaro GCC 4.8-2014.04 unknown) ) #1 SMP Fri Apr 20 15:17:54 CST 2018
[ 0.000000]
[ 0.000000] The CPU feqenuce set to 880 MHz
[ 0.000000] GCMP present
[ 0.000000] CPU0 revision is: 0001992f (MIPS 1004Kc)
[ 0.000000] Software DMA cache coherency
[ 0.000000] Determined physical RAM map:
[ 0.000000] memory: 08000000 @ 00000000 (usable)
[ 0.000000] Initrd not found or empty - disabling initrd
[ 0.000000] Zone ranges:
[ 0.000000] DMA [mem 0x00000000-0x00ffffff]
[ 0.000000] Normal [mem 0x01000000-0x07ffffff]
[ 0.000000] Movable zone start for each node
[ 0.000000] Early memory node ranges
[ 0.000000] node 0: [mem 0x00000000-0x07ffffff]
[ 0.000000] Detected 3 available secondary CPU(s)
[ 0.000000] Primary instruction cache 32kB, 4-way, VIPT, linesize 32 bytes.
[ 0.000000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
[ 0.000000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
[ 0.000000] PERCPU: Embedded 7 pages/cpu @819ae000 s6656 r8192 d13824 u32768
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 32512
[ 0.000000] Kernel command line: console=ttyS1,57600n8 root=/dev/mtdblock6 rootfstype=squashfs,jffs2
[ 0.000000] PID hash table entries: 512 (order: -1, 2048 bytes)
[ 0.000000] Dentry cache hash table entries: 16384 (order: 4, 65536 bytes)
[ 0.000000] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)
[ 0.000000] Writing ErrCtl register=00023223
[ 0.000000] Readback ErrCtl register=00023223
[ 0.000000] Memory: 120936k/131072k available (5489k kernel code, 10136k reserved, 2360k data, 272k init, 0k highmem)
[ 0.000000] Hierarchical RCU implementation.
[ 0.000000] NR_IRQS:128
[ 0.000000] console [ttyS1] enabled
[ 0.120000] Calibrating delay loop... 577.53 BogoMIPS (lpj=1155072)
[ 0.160000] pid_max: default: 32768 minimum: 301
[ 0.164000] Mount-cache hash table entries: 512
[ 0.168000] launch: starting cpu1
[ 0.172000] launch: cpu1 gone!
[ 0.172000] CPU1 revision is: 0001992f (MIPS 1004Kc)
[ 0.172000] Primary instruction cache 32kB, 4-way, VIPT, linesize 32 bytes.
[ 0.172000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
[ 0.172000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
[ 0.204000] Synchronize counters for CPU 1: done.
[ 0.212000] launch: starting cpu2
[ 0.216000] launch: cpu2 gone!
[ 0.216000] CPU2 revision is: 0001992f (MIPS 1004Kc)
[ 0.216000] Primary instruction cache 32kB, 4-way, VIPT, linesize 32 bytes.
[ 0.216000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
[ 0.216000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
[ 0.248000] Synchronize counters for CPU 2: done.
[ 0.256000] launch: starting cpu3
[ 0.260000] launch: cpu3 gone!
[ 0.260000] CPU3 revision is: 0001992f (MIPS 1004Kc)
[ 0.260000] Primary instruction cache 32kB, 4-way, VIPT, linesize 32 bytes.
[ 0.260000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
[ 0.260000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
[ 0.288000] Synchronize counters for CPU 3: done.
[ 0.296000] Brought up 4 CPUs
[ 0.300000] NET: Registered protocol family 16
[ 0.600000] release PCIe RST: RALINK_RSTCTRL = 7000000
[ 0.604000] PCIE PHY initialize
[ 0.608000] ***** Xtal 40MHz *****
[ 0.612000] start MT7621 PCIe register access
[ 1.204000] RALINK_RSTCTRL = 7000000
[ 1.208000] RALINK_CLKCFG1 = 77ffeff8
[ 1.212000]
[ 1.212000] *************** MT7621 PCIe RC mode *************
大佬帮忙看下什么故障
-----------------------------------------------------------------------------------------------------------分割线
还有OPboot下的TTL信息
Warning: WPS button wasn't pressed or not long enough!
Warning normal boot...
0
3: System Boot system code via Flash.
## Checking image at bc050000 ...
Image Name: MIPS OpenWrt Linux-5.4.102
Image Type: MIPS Linux Kernel Image (lzma compressed)
Data Size: 2496370 Bytes = 2.4 MB
Load Address: 80001000
Entry Point: 80001000
Uncompressing Kernel Image ... LZMA ERROR 1 - must RESET board to recover
===================================================================
MT7621 stage1 code Mar 12 2015 14:43:30 (ASIC)
CPU=500000000 HZ BUS=166666666 HZ
==================================================================
Change MPLL source from XTAL to CR...
do MEMPLL setting..
MEMPLL Config : 0x11100000
3PLL mode + External loopback
=== XTAL-40Mhz === DDR-1200Mhz ===
PLL3 FB_DL: 0x8, 1/0 = 724/300 21000000
PLL2 FB_DL: 0x12, 1/0 = 729/295 49000000
PLL4 FB_DL: 0x1b, 1/0 = 573/451 6D000000
do DDR setting..[01F40000]
Apply DDR3 Setting...(use customer AC)
0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120
--------------------------------------------------------------------------------
0000:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0001:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0002:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0003:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0004:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0005:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0006:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0007:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0008:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0009:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000A:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000B:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000C:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000D:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000E:| 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
000F:| 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0
0010:| 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0
0011:| 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
0012:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0013:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0014:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0015:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0016:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0017:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0018:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0019:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001A:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001B:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001C:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001D:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001E:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001F:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DRAMC_DQSCTL1[0e0]=13000000
DRAMC_DQSGCTL[124]=80000033
rank 0 coarse = 15
rank 0 fine = 72
B:| 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0
opt_dle value:9
DRAMC_DDR2CTL[07c]=C287221D
DRAMC_PADCTL4[0e4]=000022B3
DRAMC_DQIDLY1[210]=0A09090A
DRAMC_DQIDLY2[214]=06090907
DRAMC_DQIDLY3[218]=09070805
DRAMC_DQIDLY4[21c]=09060907
DRAMC_R0DELDLY[018]=00002122
==================================================================
RX DQS perbit delay software calibration
==================================================================
1.0-15 bit dq delay value
==================================================================
bit| 0 1 2 3 4 5 6 7 8 9
--------------------------------------
0 | 8 6 7 10 6 7 7 5 4 6
10 | 7 8 7 8 6 8
--------------------------------------
==================================================================
2.dqs window
x=pass dqs delay value (min~max)center
y=0-7bit DQ of every group
input delayQS0 =34 DQS1 = 33
==================================================================
bit DQS0 bit DQS1
0 (1~64)32 8 (1~63)32
1 (0~62)31 9 (1~62)31
2 (1~64)32 10 (1~66)33
3 (1~67)34 11 (1~64)32
4 (1~65)33 12 (1~66)33
5 (1~64)32 13 (1~63)32
6 (1~64)32 14 (1~65)33
7 (1~66)33 15 (1~63)32
==================================================================
3.dq delay value last
==================================================================
bit| 0 1 2 3 4 5 6 7 8 9
--------------------------------------
0 | 10 9 9 10 7 9 9 6 5 8
10 | 7 9 7 9 6 9
==================================================================
==================================================================
TX perbyte calibration
==================================================================
DQS loop = 15, cmp_err_1 = ffff0000
dqs_perbyte_dly.last_dqsdly_pass[0]=15, finish count=1
dqs_perbyte_dly.last_dqsdly_pass[1]=15, finish count=2
DQ loop=15, cmp_err_1 = ffff01a2
DQ loop=14, cmp_err_1 = ffff0000
dqs_perbyte_dly.last_dqdly_pass[0]=14, finish count=1
dqs_perbyte_dly.last_dqdly_pass[1]=14, finish count=2
byte:0, (DQS,DQ)=(8,8)
byte:1, (DQS,DQ)=(8,8)
DRAMC_DQODLY1[200]=88888888
DRAMC_DQODLY2[204]=88888888
20,data:88
[EMI] DRAMC calibration passed
===================================================================
MT7621 stage1 code done
CPU=500000000 HZ BUS=166666666 HZ
===================================================================
1.0.8 (Jul 30 2018 - 08:03:32)
Board: MediaTek APSoC DRAM: 128 MB
Config XHCI 40M PLL
******************************
Software System Reset Occurred
******************************
MediaTek SPI flash driver, SPI clock: 31MHz
spi device id: c8 40 18 c8
Warning: un-recognized chip ID, please update bootloader!
*** Warning - bad CRC, using default environment 红色字体翻译一下
============================================
MediaTek Version: 5.0.0.3
--------------------------------------------
ASIC MT7621A DualCore (MAC to MT7530 Mode)
DRAM_CONF_FROM: Auto-Detection
DRAM_TYPE: DDR3
DRAM bus: 16 bit
Xtal Mode=3 OCP Ratio=1/3
Flash component: SPI Flash
Date:Jul 30 2018 Time:08:03:32
============================================
icache: sets:256, ways:4, linesz:32, total:32768
dcache: sets:256, ways:4, linesz:32, total:32768
#### The CPU freq = 880 MHZ ####
estimate memory size = 128 Mbytes
reset MT7530
set LAN/WAN LLLLW
-----------------------------------------------------
Mleaf OpBoot: 1.0.8
Author: Mleaf
Mail:350983773@qq.com or mleaf90@gmail.com
Date: 2017-06-03
-----------------------------------------------------
Please press WPS button for more than 3 seconds to run web failsafe mode
WPS button is pressed for: 0 second(s)
Warning: WPS button wasn't pressed or not long enough!
Warning normal boot...
感谢各位大佬
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