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下面这段提取出来的的是dtb信息吗?我看跟其他型号的格式差别很大
- {
- compatible = "mediatek,mt7981", "mediatek,mt7981-rfb";
- interrupt-parent = <0x00000001>;
- #address-cells = <0x00000001>;
- #size-cells = <0x00000001>;
- model = "mt7981-rfb";
- cpus {
- #address-cells = <0x00000001>;
- #size-cells = <0x00000000>;
- cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x00000000>;
- };
- cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x00000001>;
- };
- };
- gpt_dummy20m {
- compatible = "fixed-clock";
- clock-frequency = <0x00c65d40>;
- #clock-cells = <0x00000000>;
- u-boot,dm-pre-reloc;
- phandle = <0x00000002>;
- };
- timer {
- compatible = "arm,armv8-timer";
- interrupt-parent = <0x00000001>;
- clock-frequency = <0x00c65d40>;
- interrupts = <0x00000001 0x0000000d 0x00000008 0x00000001 0x0000000e 0x00000008 0x00000001 0x0000000b 0x00000008 0x00000001 0x0000000a 0x00000008>;
- arm,cpu-registers-not-fw-configured;
- };
- timer@10008000 {
- compatible = "mediatek,mt7986-timer";
- reg = <0x10008000 0x00001000>;
- interrupts = <0x00000000 0x00000082 0x00000004>;
- clocks = <0x00000002>;
- clock-names = "gpt-clk";
- u-boot,dm-pre-reloc;
- };
- watchdog@1001c000 {
- compatible = "mediatek,mt7986-wdt";
- reg = <0x1001c000 0x00001000>;
- interrupts = <0x00000000 0x0000006e 0x00000004>;
- #reset-cells = <0x00000001>;
- status = "disabled";
- };
- interrupt-controller@c000000 {
- compatible = "arm,gic-v3";
- #interrupt-cells = <0x00000003>;
- interrupt-parent = <0x00000001>;
- interrupt-controller;
- reg = <0x0c000000 0x00040000 0x0c080000 0x00200000>;
- interrupts = <0x00000001 0x00000009 0x00000004>;
- phandle = <0x00000001>;
- };
- apmixedsys@1001e000 {
- compatible = "mediatek,mt7981-fixed-plls";
- reg = <0x1001e000 0x00001000>;
- #clock-cells = <0x00000001>;
- u-boot,dm-pre-reloc;
- phandle = <0x00000003>;
- };
- topckgen@1001b000 {
- compatible = "mediatek,mt7981-topckgen";
- reg = <0x1001b000 0x00001000>;
- clock-parent = <0x00000003>;
- #clock-cells = <0x00000001>;
- u-boot,dm-pre-reloc;
- phandle = <0x00000005>;
- };
- infracfg_ao@10001000 {
- compatible = "mediatek,mt7981-infracfg_ao";
- reg = <0x10001000 0x00000080>;
- clock-parent = <0x00000004>;
- #clock-cells = <0x00000001>;
- u-boot,dm-pre-reloc;
- phandle = <0x00000006>;
- };
- infracfg@10001000 {
- compatible = "mediatek,mt7981-infracfg";
- reg = <0x10001000 0x00000030>;
- clock-parent = <0x00000005>;
- #clock-cells = <0x00000001>;
- u-boot,dm-pre-reloc;
- phandle = <0x00000004>;
- };
- pinctrl@11d00000 {
- compatible = "mediatek,mt7981-pinctrl";
- reg = <0x11d00000 0x00001000 0x11c00000 0x00001000 0x11c10000 0x00001000 0x11d20000 0x00001000 0x11e00000 0x00001000 0x11e20000 0x00001000 0x11f00000 0x00001000 0x11f10000 0x00001000 0x1000b000 0x00001000>;
- reg-names = "gpio_base", "iocfg_rt_base", "iocfg_rm_base", "iocfg_rb_base", "iocfg_lb_base", "iocfg_bl_base", "iocfg_tm_base", "iocfg_tl_base", "eint";
- gpio-controller {
- gpio-controller;
- #gpio-cells = <0x00000002>;
- phandle = <0x0000000b>;
- };
- spi0-pins-func-1 {
- phandle = <0x0000000c>;
- mux {
- function = "flash";
- groups = "spi0", "spi0_wp_hold";
- };
- conf-pu {
- pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
- drive-strength = <0x00000008>;
- bias-pull-up = <0x00000067>;
- };
- conf-pd {
- pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
- drive-strength = <0x00000008>;
- bias-pull-down = <0x00000067>;
- };
- };
- spi1-pins-func-1 {
- mux {
- function = "spi";
- groups = "spi1_1";
- };
- };
- spi1-pins-func-3 {
- phandle = <0x00000008>;
- mux {
- function = "uart";
- groups = "uart1_2";
- };
- };
- one-pwm-pins {
- mux {
- function = "pwm";
- groups = "pwm0_1";
- };
- };
- two-pwm-pins {
- phandle = <0x00000007>;
- mux {
- function = "pwm";
- groups = "pwm0_1", "pwm1_0";
- };
- };
- three-pwm-pins {
- mux {
- function = "pwm";
- groups = "pwm0_1", "pwm1_0", "pwm2";
- };
- };
- };
- pwm@10048000 {
- compatible = "mediatek,mt7981-pwm";
- reg = <0x10048000 0x00001000>;
- #clock-cells = <0x00000001>;
- #pwm-cells = <0x00000002>;
- interrupts = <0x00000000 0x00000089 0x00000004>;
- clocks = <0x00000004 0x00000005 0x00000006 0x0000002d 0x00000006 0x00000003 0x00000006 0x00000004 0x00000006 0x00000004>;
- assigned-clocks = <0x00000005 0x00000051>;
- assigned-clock-parents = <0x00000005 0x00000000>;
- clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <0x00000007>;
- };
- serial@11002000 {
- compatible = "mediatek,hsuart";
- reg = <0x11002000 0x00000400>;
- interrupts = <0x00000000 0x0000007b 0x00000004>;
- clocks = <0x00000006 0x00000012>;
- assigned-clocks = <0x00000005 0x00000050 0x00000006 0x00000025>;
- assigned-clock-parents = <0x00000005 0x00000000 0x00000004 0x00000001>;
- mediatek,force-highspeed;
- status = "okay";
- u-boot,dm-pre-reloc;
- };
- serial@11003000 {
- compatible = "mediatek,hsuart";
- reg = <0x11003000 0x00000400>;
- interrupts = <0x00000000 0x0000007c 0x00000004>;
- clocks = <0x00000006 0x00000013>;
- assigned-clocks = <0x00000005 0x00000050 0x00000006 0x00000026>;
- assigned-clock-parents = <0x00000005 0x00000000 0x00000004 0x00000001>;
- mediatek,force-highspeed;
- status = "disabled";
- pinctrl-names = "default";
- pinctrl-0 = <0x00000008>;
- };
- serial@11004000 {
- compatible = "mediatek,hsuart";
- reg = <0x11004000 0x00000400>;
- interrupts = <0x00000000 0x0000007c 0x00000004>;
- clocks = <0x00000006 0x00000014>;
- assigned-clocks = <0x00000005 0x00000050 0x00000006 0x00000027>;
- assigned-clock-parents = <0x00000005 0x00000000 0x00000004 0x00000001>;
- mediatek,force-highspeed;
- status = "disabled";
- };
- snand@11005000 {
- compatible = "mediatek,mt7986-snand";
- reg = <0x11005000 0x00001000 0x11006000 0x00001000>;
- reg-names = "nfi", "ecc";
- clocks = <0x00000006 0x00000018 0x00000006 0x00000017 0x00000006 0x00000019>;
- clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
- assigned-clocks = <0x00000005 0x0000004d 0x00000005 0x0000004c>;
- assigned-clock-parents = <0x00000005 0x00000006 0x00000005 0x00000006>;
- status = "disabled";
- };
- syscon@15000000 {
- compatible = "mediatek,mt7981-ethsys", "syscon";
- reg = <0x15000000 0x00001000>;
- clock-parent = <0x00000005>;
- #clock-cells = <0x00000001>;
- #reset-cells = <0x00000001>;
- phandle = <0x00000009>;
- };
- ethernet@15100000 {
- compatible = "mediatek,mt7981-eth", "syscon";
- reg = <0x15100000 0x00020000>;
- resets = <0x00000009 0x00000006>;
- reset-names = "fe";
- mediatek,ethsys = <0x00000009>;
- mediatek,sgmiisys = <0x0000000a>;
- #address-cells = <0x00000001>;
- #size-cells = <0x00000000>;
- status = "okay";
- mediatek,gmac-id = <0x00000000>;
- phy-mode = "sgmii";
- mediatek,switch = "mt7531";
- reset-gpios = <0x0000000b 0x00000027 0x00000000>;
- fixed-link {
- speed = <0x000003e8>;
- full-duplex;
- };
- };
- syscon@10060000 {
- compatible = "mediatek,mt7986-sgmiisys", "syscon";
- reg = <0x10060000 0x00001000>;
- pn_swap;
- #clock-cells = <0x00000001>;
- phandle = <0x0000000a>;
- };
- syscon@10070000 {
- compatible = "mediatek,mt7986-sgmiisys", "syscon";
- reg = <0x10070000 0x00001000>;
- #clock-cells = <0x00000001>;
- };
- spi@1100a000 {
- compatible = "mediatek,ipm-spi";
- reg = <0x1100a000 0x00000100>;
- clocks = <0x00000006 0x0000001a 0x00000005 0x0000004e>;
- assigned-clocks = <0x00000005 0x0000004e 0x00000004 0x00000028>;
- assigned-clock-parents = <0x00000005 0x00000002 0x00000005 0x00000002>;
- clock-names = "sel-clk", "spi-clk";
- interrupts = <0x00000000 0x0000008c 0x00000004>;
- status = "okay";
- #address-cells = <0x00000001>;
- #size-cells = <0x00000000>;
- pinctrl-names = "default";
- pinctrl-0 = <0x0000000c>;
- must_tx;
- enhance_timing;
- dma_ext;
- ipm_design;
- support_quad;
- tick_dly = <0x00000002>;
- sample_sel = <0x00000000>;
- spi_nand@0 {
- compatible = "spi-nand";
- reg = <0x00000000>;
- spi-max-frequency = <0x03197500>;
- };
- };
- spi@1100b000 {
- compatible = "mediatek,ipm-spi";
- reg = <0x1100b000 0x00000100>;
- interrupts = <0x00000000 0x0000008d 0x00000004>;
- status = "disabled";
- };
- spi@11009000 {
- compatible = "mediatek,ipm-spi";
- reg = <0x11009000 0x00000100>;
- clocks = <0x00000006 0x0000001a 0x00000005 0x0000004e>;
- assigned-clocks = <0x00000005 0x0000004e 0x00000004 0x00000028>;
- assigned-clock-parents = <0x00000005 0x00000002 0x00000005 0x00000002>;
- clock-names = "sel-clk", "spi-clk";
- interrupts = <0x00000000 0x0000008e 0x00000004>;
- status = "disabled";
- };
- mmc@11230000 {
- compatible = "mediatek,mt7981-mmc";
- reg = <0x11230000 0x00001000 0x11c20000 0x00001000>;
- interrupts = <0x00000000 0x0000008f 0x00000004>;
- clocks = <0x00000005 0x00000034 0x00000005 0x00000033 0x00000006 0x0000001f>;
- assigned-clocks = <0x00000005 0x00000055 0x00000005 0x00000054>;
- assigned-clock-parents = <0x00000005 0x0000001c 0x00000005 0x00000002>;
- clock-names = "source", "hclk", "source_cg";
- status = "disabled";
- };
- chosen {
- stdout-path = "/serial@11002000";
- tick-timer = "/timer@10008000";
- };
- memory@40000000 {
- device_type = "memory";
- reg = <0x40000000 0x10000000>;
- };
- };
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