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今天无意中看到TLL的启动信息,内存识别只有256M?然后我就刷了PB-BOOT,显示就是512M。
还是我的固件有问题?我已经升级到最新正式版本
- ===================================================================
- MT7621 stage1 code 10:33:11 (ASIC)
- CPU=50000000 HZ BUS=16666666 HZ
- ==================================================================
- Change MPLL source from XTAL to CR...
- do MEMPLL setting..
- MEMPLL Config : 0x11100000
- 3PLL mode + External loopback
- === XTAL-40Mhz === DDR-1200Mhz ===
- PLL2 FB_DL: 0x1, 1/0 = 524/500 05000000
- PLL4 FB_DL: 0xd, 1/0 = 588/436 35000000
- PLL3 FB_DL: 0x16, 1/0 = 796/228 59000000
- do DDR setting..[00320381]
- Apply DDR3 Setting...(use customer AC)
- 0 8 16 24 32 40 48 56 64 72 80 88 96 104 11 2 120
- -------------------------------------------------------------------------- ------
- 0000:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 0001:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 0002:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 0003:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 0004:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 0005:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 0006:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 0007:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 0008:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 0009:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 000A:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 000B:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 000C:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 000D:| 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
- 000E:| 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
- 000F:| 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0
- 0010:| 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0
- 0011:| 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 0012:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 0013:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 0014:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 0015:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 0016:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 0017:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 0018:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 0019:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 001A:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 001B:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 001C:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 001D:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 001E:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 001F:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- rank 0 coarse = 15
- rank 0 fine = 56
- B:| 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0
- opt_dle value:9
- DRAMC_R0DELDLY[018]=00001B1D
- ==================================================================
- RX DQS perbit delay software calibration
- ==================================================================
- 1.0-15 bit dq delay value
- ==================================================================
- bit| 0 1 2 3 4 5 6 7 8 9
- --------------------------------------
- 0 | 11 7 9 10 8 6 9 8 5 7
- 10 | 8 9 8 10 8 11
- --------------------------------------
- ==================================================================
- 2.dqs window
- x=pass dqs delay value (min~max)center
- y=0-7bit DQ of every group
- input delay:DQS0 =29 DQS1 = 27
- ==================================================================
- bit DQS0 bit DQS1
- 0 (1~56)28 8 (1~49)25
- 1 (1~52)26 9 (1~48)24
- 2 (1~50)25 10 (1~50)25
- 3 (1~54)27 11 (1~48)24
- 4 (1~54)27 12 (1~54)27
- 5 (1~54)27 13 (1~52)26
- 6 (1~54)27 14 (0~51)25
- 7 (1~57)29 15 (1~54)27
- ==================================================================
- 3.dq delay value last
- ==================================================================
- bit| 0 1 2 3 4 5 6 7 8 9
- --------------------------------------
- 0 | 12 10 13 12 10 8 11 8 7 10
- 10 | 10 12 8 11 10 11
- ==================================================================
- ==================================================================
- TX perbyte calibration
- ==================================================================
- DQS loop = 15, cmp_err_1 = ffff0000
- dqs_perbyte_dly.last_dqsdly_pass[0]=15, finish count=1
- dqs_perbyte_dly.last_dqsdly_pass[1]=15, finish count=2
- DQ loop=15, cmp_err_1 = ffff01ba
- DQ loop=14, cmp_err_1 = ffff0020
- dqs_perbyte_dly.last_dqdly_pass[1]=14, finish count=1
- DQ loop=13, cmp_err_1 = ffff0000
- dqs_perbyte_dly.last_dqdly_pass[0]=13, finish count=2
- byte:0, (DQS,DQ)=(9,8)
- byte:1, (DQS,DQ)=(8,8)
- 20,data:89
- [EMI] DRAMC calibration passed
- ===================================================================
- MT7621 stage1 code done
- CPU=50000000 HZ BUS=16666666 HZ
- ===================================================================
- U-Boot 1.1.3 (Jan 19 2017 - 17:14:12)
- Board: Ralink APSoC DRAM: 256 MB
- Power on memory test. Memory size= 256 MB...OK!
- relocate_code Pointer at: 8ffac000
- Config XHCI 40M PLL
- Allocate 16 byte aligned buffer: 8ffe0050
- Enable NFI Clock
- # MTK NAND # : Use HW ECC
- NAND ID [C8 DA 90 95 44]
- Device found in MTK table, ID: c8da, EXT_ID: 909544
- Support this Device in MTK table! c8da
- select_chip
- [NAND]select ecc bit:4, sparesize :64 spare_per_sector=16
- Signature matched and data read!
- load_fact_bbt success 2047
- load fact bbt success
- [mtk_nand] probe successfully!
- mtd->writesize=2048 mtd->oobsize=64, mtd->erasesize=131072 devinfo.iowidth=8
- ..============================================
- Ralink UBoot Version: 5.0.0.0
- --------------------------------------------
- ASIC MT7621A DualCore (MAC to MT7530 Mode)
- DRAM_CONF_FROM: Auto-Detection
- DRAM_TYPE: DDR3
- DRAM bus: 16 bit
- Xtal Mode=3 OCP Ratio=1/3
- Flash component: NAND Flash
- Date:Jan 19 2017 Time:17:14:12
- ============================================
- icache: sets:256, ways:4, linesz:32 ,total:32768
- dcache: sets:256, ways:4, linesz:32 ,total:32768
- ##### The CPU freq = 880 MHZ ####
- estimate memory size =256 Mbytes
- #Reset_MT7530
- set LAN/WAN LLLLW
- Please choose the operation:
- 1: Load system code to SDRAM via TFTP.
- 2: Load system code then write to Flash via TFTP.
- 3: Boot system code via Flash (default).
- 4: Entr boot command line interface.
- 7: Load Boot Loader code then write to Flash via Serial.
- 9: Load Boot Loader code then write to Flash via TFTP.
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