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和wmc181,wuc181都是同一个有ttl接口
拆解图
无线部分为7905+7975
- 部分ttl输出
- 000D:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 000E:| 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
- 000F:| 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0
- 0010:| 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0
- 0011:| 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
- 0012:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 0013:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 0014:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 0015:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 0016:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 0017:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 0018:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 0019:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 001A:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 001B:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 001C:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 001D:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 001E:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 001F:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- DRAMC_DQSCTL1[0e0]=14000000
- DRAMC_DQSGCTL[124]=80000000
- rank 0 coarse = 16
- rank 0 fine = 40
- B:| 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0
- opt_dle value:9
- DRAMC_DDR2CTL[07c]=C287221D
- DRAMC_PADCTL4[0e4]=000022B3
- DRAMC_DQIDLY1[210]=0D0B090B
- DRAMC_DQIDLY2[214]=080A0808
- DRAMC_DQIDLY3[218]=0B090708
- DRAMC_DQIDLY4[21c]=0A090908
- DRAMC_R0DELDLY[018]=00001F20
- ==================================================================
- RX DQS perbit delay software calibration
- ==================================================================
- 1.0-15 bit dq delay value
- ==================================================================
- bit| 0 1 2 3 4 5 6 7 8 9
- --------------------------------------
- 0 | 10 9 10 12 7 7 8 8 7 6
- 10 | 9 8 7 9 9 9
- --------------------------------------
- ==================================================================
- 2.dqs window
- x=pass dqs delay value (min~max)center
- y=0-7bit DQ of every group
- input delay:DQS0 =32 DQS1 = 31
- ==================================================================
- bit DQS0 bit DQS1
- 0 (1~62)31 8 (1~60)30
- 1 (1~63)32 9 (1~60)30
- 2 (1~62)31 10 (1~62)31
- 3 (1~62)31 11 (0~57)28
- 4 (0~62)31 12 (1~59)30
- 5 (1~62)31 13 (2~60)31
- 6 (0~61)30 14 (1~62)31
- 7 (1~64)32 15 (2~58)30
- ==================================================================
- 3.dq delay value last
- ==================================================================
- bit| 0 1 2 3 4 5 6 7 8 9
- --------------------------------------
- 0 | 11 9 11 13 8 8 10 8 8 7
- 10 | 9 11 8 9 9 10
- ==================================================================
- ==================================================================
- TX perbyte calibration
- ==================================================================
- DQS loop = 15, cmp_err_1 = ffff0000
- dqs_perbyte_dly.last_dqsdly_pass[0]=15, finish count=1
- dqs_perbyte_dly.last_dqsdly_pass[1]=15, finish count=2
- DQ loop=15, cmp_err_1 = ffff0000
- dqs_perbyte_dly.last_dqdly_pass[0]=15, finish count=1
- dqs_perbyte_dly.last_dqdly_pass[1]=15, finish count=2
- byte:0, (DQS,DQ)=(8,8)
- byte:1, (DQS,DQ)=(8,8)
- DRAMC_DQODLY1[200]=88888888
- DRAMC_DQODLY2[204]=88888888
- 20,data:88
- [EMI] DRAMC calibration passed
- ===================================================================
- MT7621 stage1 code done
- CPU=50000000 HZ BUS=16666666 HZ
- ===================================================================
- U-Boot 1.1.3 (Mar 19 2021 - 16:31:52)
- Board: Ralink APSoC DRAM: 256 MB
- relocate_code Pointer at: 8ff98000
- set ALL LAN Partition
- Config XHCI 40M PLL
- Allocate 16 byte aligned buffer: 8ffe0790
- Enable NFI Clock
- # MTK NAND # : Use HW ECC
- NAND ID [C8 D1 80 95 40]
- Device not found, ID: c8d1
- Not Support this Device!
- chip_mode=00000001
- Support this Device in MTK table! c8d1
- select_chip
- [NAND]select ecc bit:4, sparesize :64 spare_per_sector=16
- Signature matched and data read!
- load_fact_bbt success 1023
- load fact bbt success
- [mtk_nand] probe successfully!
- mtd->writesize=2048 mtd->oobsize=64, mtd->erasesize=131072 devinfo.iowidth=8
- .*** Warning - bad CRC, using default environment
- Press reset button to enter recovery mode.
- Autobooting in 300 ms
- Dual image validation, to check image_1 now
- #Reset_MT7530
- verifying uboot partition...
- ..ok
- verifying kernel and romfs partition...
- ................................................................................................................................................................ok
- Dual image validation, image_1 pass. So boot to image_1
- ..normal boot offset = 585000, size = 20000
- ..To boot, bootcmd = bootm 0xa0800000.
- ..normal boot offset = 585000, size = 20000
- ..
- U-Boot 1.1.3 (Mar 19 2021 - 17:01:05)
- Board: Ralink APSoC DRAM: 256 MB
- relocate_code Pointer at: 8ffb0000
- Config XHCI 40M PLL
- Allocate 16 byte aligned buffer: 8ffe0530
- Enable NFI Clock
- # MTK NAND # : Use HW ECC
- NAND ID [C8 D1 80 95 40]
- Device not found, ID: c8d1
- Not Support this Device!
- chip_mode=00000001
- Support this Device in MTK table! c8d1
- select_chip
- [NAND]select ecc bit:4, sparesize :64 spare_per_sector=16
- Signature matched and data read!
- load_fact_bbt success 1023
- load fact bbt success
- [mtk_nand] probe successfully!
- mtd->writesize=2048 mtd->oobsize=64, mtd->erasesize=131072 devinfo.iowidth=8
- .*** Warning - bad CRC, using default environment
- ============================================
- Ralink UBoot Version: 4.3.S.0
- --------------------------------------------
- ASIC MT7621A DualCore (MAC to MT7530 Mode)
- DRAM_CONF_FROM: Auto-Detection
- DRAM_TYPE: DDR3
- DRAM bus: 16 bit
- Xtal Mode=3 OCP Ratio=1/3
- Flash component: NAND Flash
- Date:Mar 19 2021 Time:17:01:05
- ============================================
- icache: sets:256, ways:4, linesz:32 ,total:32768
- dcache: sets:256, ways:4, linesz:32 ,total:32768
- ##### The CPU freq = 880 MHZ ####
- estimate memory size =256 Mbytes
- #Reset_MT7530
- set ALL LAN Partition
- Booting image_1(kernel_1)To boot and runcmd bootm 0x006c0000.
- Autobooting in 0 ms
- ## Booting image at 006c0000 ...
- addr:0x006c0000
- ..
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